NB7V52M Datasheet(PDF) - ON Semiconductor
Schematic timing diagram of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
a) PFD Model, (b) Implementation of D- Flip Flop with Nor gates, (c)... | Download Scientific Diagram
Current-Mode-Logic (CML) Latch | EveryNano Counts
PDF) Novel Differential-Mode RTD/HBT MOBILE-based D-Flip Flop IC
PDF) Low-power high-speed performance of current-mode logic D flip-flop topology using negative-differential-resistance devices
An improved current mode logic latch for high‐speed applications - Kumawat - 2020 - International Journal of Communication Systems - Wiley Online Library
PDF) Low-power high-speed performance of current-mode logic D flip-flop topology using negative-differential-resistance devices
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
adding reset function to D Flip FLOP | Forum for Electronics
NB7V52M - D Flip Flop, 1.8 V / 2.5 V Differential, with Reset and CML Outputs
Analysis and Design of High-Speed CMOS Frequency Dividers
Circuit Design (GPS) Part 6
NB7V52M Flip-Flop Datasheet pdf - D Flip-Flop. Equivalent, Catalog
adding reset function to D Flip FLOP | Forum for Electronics
Circuit configuration of the CML-type SR-latch circuit a Circuit... | Download Scientific Diagram
PDF) A novel ultra high-speed flip-flop-based frequency divider | Payam Heydari - Academia.edu
DFF-based CMOS clock divider. | Download Scientific Diagram
adding reset function to D Flip FLOP | Forum for Electronics
![PDF] New RTD-based set/reset latch IC for high-speed mobile D-flip flops | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/a9f1b39596e7f08405b62eebe623914a1e5c78d1/2-Figure2-1.png "PDF] New RTD-based set/reset latch IC for high-speed mobile D-flip flops | Semantic Scholar")
PDF] New RTD-based set/reset latch IC for high-speed mobile D-flip flops | Semantic Scholar
